In a semiconductor integrated circuit device using a CMOS logic gate, as a technique for reducing the power dissipation, it is effective to use “dynamic voltage and frequency scaling (DVFS)” that controls the power source voltage depending on the speed required thereof. In the case of using the DVFS, in order to enhance the effect of reducing the power dissipation, it is needed to control the power source voltage in a possible shortest period of time with a possible highest accuracy, after the required operational speed (clock frequency) is changed.
As the techniques for the power-source-voltage control in the DVFS, there is a technique that controls the voltage in accordance with the result of comparison between the operational speed of the circuit and the required operational speed while using a speed monitor, as described in JP-2001-244421A. In the same publication, there is also a description that a conversion table between the power source voltage and the operational speed is prepared in advance, and the circuit immediately shifts to an optimum power source voltage in accordance with the required operational speed.
In order to change the power source voltage to the optimum voltage within a short period of time, it is needed to accelerate the rate of changing the power source voltage, i.e., power-source-voltage control rate. However, an excessively higher power-source-voltage control rate, if employed, delays the feedback from the speed monitor to the power-source-voltage control circuit, such as a regulator, whereby the controlled power source voltage may oscillate in the vicinity of the optimum voltage, and may delay the convergence to the optimum voltage. Or else, the convergence may not be achieved.
On the other hand, a lower power-source-voltage control rate, if employed, prolongs the time length needed for control of the power source voltage to the optimum voltage after the change of speed if the operational speed is largely changed, i.e., the difference between the optimum voltages is larger.
In JP-2001-244421A, the above problem is solved by controlling the power-source-voltage control rate based on the result of comparison with the reference speed by the speed monitor. However, in this technique, the main object thereof is to reduce the time length during which the operational speed is insufficient, by rapidly increasing the power source voltage if the power source voltage is lower than the minimum voltage that is required of the power source voltage. Thus, it is impossible to satisfy the request of controlling to the optimum voltage with a higher accuracy. In the case of controlling the change rate of the power source voltage based on the conversion table, there is also the problem that a larger number of conversion tables are needed in advance corresponding to the difference in the environment, such as the temperature.